3D IC Design Flow

Recently I got a question from one of the visitors of my webpage:

“How can I perform a 3D IC design?”

So, I decided to have a post here to answer some questions that people can have.


Basic Concept

Designing a 3D IC can mean various things. For someone, it can be designing analog circuits, and it maybe designing digital or high-frequency (RF) circuits. Whatever it is, normally what you need is a firm netlist of the design that you wish to perform. It could be either

  • Verilog (.v or .vhdl)
  • SPICE (.sp or any relevant type)

or any type that describe the hardware of your design.

With the netlist you have, you need to somehow cut your design into two, three, or more (based on your 3D design: 2-tier?…3-tier? or more?…). We call this ‘partitioning’. Once the partitioning is done, it would be all about using the tools you are familiar to design your circuit. Of course, many significant details are not described how to partition or how to design your partitioned circuits, but this is the very basic concept you need to understand.

Design Tools

If someone knows the complexity that a typical design has, he (or she) would definitely know that proper tools are needed to design these 3D ICs. For example, if we are performing a digital design, we would need a tool that could “Synthesize” the RTL (registor-transistor-level schematic) into gated netlist. Also, we need a “Partitioner” that could partition the design into two, three, or more dies. Finally, once the netlist is partitioned, the design would need to be placed and routed. There are many companies that provide tools to do this (e.g., Cadence, Synopsys, Mentor Graphics).

  • Synthesis
    • RTL compiler (Cadence)
    • Design compiler (Synopsys)
    • Real-time designer (Mentor Graphics)
  • Place and Route
    • Encounter (Cadence)
    • IC compiler (Synopsys)
    • Calibre In-route (Mentor Graphics)

However, partitioning is a step that just using commercial tools would not help. If we want to make a 3D design, we need to decide locations for TSVs or any face-to-face connections that we want to make. Some companies have tools to do this, but it has not been released to public. For my case, I use an in-house tool that has been developed from our group.

Analysis Tools

Once the design is done, a designer must do various analysis. Starting from timing analysis (delay), power analysis, and reliability analysis, many kinds of analysis must be performed to check whether the design is done correctly. Since there are many different analysis tools that can do the work for this, i’ll skip the listing.


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