Until now, I’ve participated in the following research topics:

  • Low-power design methodologies for 3D ICs – with Intel (2012-current)
  • Parasitic extraction of 3D ICs: TSV and F2F (face-to-face) (2014-2015)
  • Full-chip impact of CNFET ICs – with Stanford Univ. (2013-2014)
  • Multi-TSV (through silicon via) to TSV coupling analysis on 3D IC (2013)
  • 3D IC-package-board co-analysis methodology for 3D EM simulation – with CST (2012)
  • Thermal analysis methodology of 3D ICs with integrated voltage regulators – with Columbia Univ. (2012)
  • Chip, package, PCB co-IR-drop analysis of silicon interposer on 3D IC (2011)
  • Shielding design in on-line electric vehicle (OLEV) (2010)
  • 2.5D silicon interposer design considering SI/PI (2009)
  • EMI / EMC on DC/DC converters (2008)

Details of my research will be posted through my Blog.

Print Friendly, PDF & Email

Leave a Reply

Your email address will not be published. Required fields are marked *